Two transistor silicon-oxide-nitride-oxide-silicon memory devices (“2T SONOS”) can tolerate a greater variation in the erase threshold voltage (Vt) distribution of individual memory cells, due to the use of an additional select transistor. It is not necessary to adjust the erase threshold voltages on a column by column basis in such devices. However, the erase threshold voltage distribution is not tight enough to make a one transistor (“1T SONOS”) device functional. Due to a large variation of SONOS device characteristics within a given memory row, existing techniques do not significantly tighten the distribution of erase threshold voltages within a sector. For many advanced technologies (130 nm and below), random dopant fluctuation is a significant source of Vt variation. For these technologies, the Vt distribution within a WL is naturally very broad—and in fact can be almost as broad as the distribution of Vt within the full chip.